1. Field of the Invention
The present invention relates to a semiconductor integrated circuit which operates in synchronization with a clock signal and, more particularly, to a semiconductor integrated circuit having a receiving circuit of an input signal. Further, the present invention relates to a semiconductor integrated circuit having a memory array.
2. Description of the Related Art
The amount of data used in portable equipment such as a cellular phone has been yearly increasing. Accordingly, there has been needed a semiconductor memory with large capacity and high speed to be mounted on the portable equipment. A DRAM of a clock synchronous type such as SDRAM (Synchronous DRAM) is a promising semiconductor memory to be mounted on portable equipment of this kind because of its large capacity and high speed.
Meanwhile, the portable equipment operates with a battery. Hence, electronic parts mounted on the portable electronic equipment are required to have low power consumption. Particularly, since the cellular phone is often used outdoors for a long period of time, low power consumption during standby is of significance.
It is considered that, a standby current of the SDRAM is mainly charge and discharge current which occurs along with oscillation of a clock signal generated in circuits for receiving a clock signal. Hence, the standby current of the SDRAM increases in proportion to the frequency of the clock signal to be supplied. Therefore, there has been a tendency to avoid mounting the semiconductor integrated circuit of the clock synchronous type such as the SDRAM on the portable equipment with high operation frequency despite of its large capacity and high speed.
It is an object of the present invention to reduce a standby current of a semiconductor integrated circuit of a clock synchronous type.
Particularly, it is an object of the present invention to provide a circuit technique for minimizing increase in the standby current when the frequency of a clock signal increases.
According to one of the aspects of the semiconductor integrated circuit of the present invention, a timing signal generator receives a plurality of control signals in synchronization with a clock signal and generates a timing signal according to a combination of the control signals. A delay circuit delays an input signal received asynchronously to the clock signal by a predetermined time. A receiving circuit receives the input signal delayed by the delay circuit, in synchronization not with the clock signal but with the timing signal. Namely, the receiving circuit operates asynchronously to the clock signal, and receives only necessary input signals for the internal operation of the semiconductor integrated circuit.
When a combination of the control signals is not the one for generating the timing signal, the timing signal is not generated, and hence the receiving circuit does not operate. Operation frequency of the receiving circuit decreases, thereby reducing power consumption of the receiving circuit. A decrease in the number of the circuits operating in synchronization with the clock signal enables a reduction in current consumption (standby current) particularly during a standby mode in which an internal circuit is not operated. Since the number of the circuits operating in synchronization with the clock signal is small, an increase in the standby current is gradual even when the frequency of the clock signal increases.
According to another aspect of the semiconductor integrated circuit of the present invention, an input buffer receives the input signal asynchronously to the clock signal and outputs the received signal to the delay circuit. Hence, the input signal is transmitted to the receiving circuit asynchronously to the clock signal. Since the number of the circuits operating in synchronization with the clock signal can be reduced, it is possible to reduce the standby current.
According to another aspect of the semiconductor integrated circuit of the present invention, the receiving circuit receives an address signal. The address signal is normally composed of a plurality of bits in order to identify one of a plurality of areas in the semiconductor integrated circuit. It is necessary to provide the receiving circuit for each bit of the address signal. Therefore, the receiving circuit receiving the address signal realizes a substantial reduction in the standby current.
According to another aspect of the semiconductor integrated circuit of the present invention, the receiving circuit receives a data signal. The data signal is normally composed of a plurality of bits in order to increase a data transfer rate. The receiving circuit is required to be provided for each bit of the data signal. Therefore, the receiving circuit receiving the data signal realizes a substantial reduction in the standby current.
According to another aspect of the semiconductor integrated circuit of the present invention, the timing signal generator receives a plurality of command signals in synchronization with the clock signal and generates the timing signal for instructing operation of a memory array according to the combination of the command signals. The receiving circuit receives the address signal for identifying a memory cell in the memory array, in synchronization with the timing signal. Further, a predetermined memory cell corresponding to the address signal is selected from a plurality of the memory cells in the memory array, and read operation or the like is performed.
The address signal is generally composed of a large number of bits in order to select any of the plurality of memory cells in the memory array. The receiving circuit is required to be provided for each bit of the address signal. Therefore, the standby current can be substantially reduced by applying the present invention to the semiconductor integrated circuit having the memory array.
According to another aspect of the semiconductor integrated circuit of the present invention, a delay time of the delay circuit is set corresponding to a time from reception of the command signal to output of the timing signal by the timing signal generator. In the semiconductor integrated circuit of the clock synchronous type (semiconductor memory), the command signal and the address signal are generally supplied from the exterior of the integrated circuit, in synchronization with the same edge of the clock signal. Namely, the command signal and the address signal are supplied so as to satisfy set-up time and hold time with respect to the edge of the clock signal. Hence, setting the delay time according to the time taken for generating the timing signal from the command signal enables concurrent arrival of the timing signal and the address signal in the receiving circuit. This makes it possible to reliably receive the address signal supplied with the command signal in the receiving circuit, in synchronization with the clock signal.